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ICS673-01 PLL Building Block
Description
The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (easily implemented with the ICS674-01), the user can easily customize the clock to lock to a wide variety of input frequencies. Included on the ICS673-01 are an Output Enable function that puts both outputs into a highimpedance state, as well as a Power Down feature that turns off the entire device.
Features
* Packaged in 16 pin narrow SOIC * Access to VCO input and feedback paths of PLL * VCO operating range up to 135 MHz (5V) * Able to lock MHz range outputs to kHz range inputs through use of external dividers * Output Enable tri-states outputs * Low skew output clocks * Power Down turns off chip * VCO predivide of 1 or 4 * 25 mA output drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * +3.3 V 5% or +5 V 10% operating voltage * Industrial Temperature range available * With the ICS674-01, forms a complete PLL
Block Diagram
VDD GND 2 3 CHGP
VDD
VCOIN
REFIN
UP
Ic
FBIN
Phase/ Frequency DOWN Detector
Ic
VCO
/4
1 MUX 0 /2
Output Buffer
CLK1
PD (entire chip)
Output Buffer
CLK2
CAP
SEL
OE (both outputs)
1 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
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ICS673-01 PLL Building Block
Pin Assignment
ICS673-01
FBIN VDD VDD GND GND GND CHGP VCOIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 REFIN NC CLK1 CLK2 PD SEL OE CAP VCO Predivide Select Table
SEL 0 1 VCO Predivide 4 1
0 = connect pin directly to ground 1 = connect pin directly to VDD
16 pin narrow (150 mil) SOIC Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name FBIN VDD VDD GND GND GND CHGP VCOIN CAP OE SEL PD CLK2 CLK1 NC REFIN Type CI P P P P P O I I I I I O O CI Description FeedBack INput. Connect feedback clock to this pin. Falling edge triggered. VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3. VDD. Connect to VDD on pin 2. Connect to ground. Connect to ground. Connect to ground. CHarGe Pump output. Connect to VCOIN under normal operation. Input to internal VCO. Loop filter return. Output Enable. Active high. Tri-states both outputs when low. SELect pin for VCO pre-divide per table above. Power Down. Turns off entire chip when this pin is low. Outputs stop low. CLocK output 2. This is a low-skew divide by two version of CLK1. CLocK output 1. No Connect. Nothing is connected internally to this pin. REFerence INput. Connect reference clock to this pin. Falling edge triggered.
Key: CI = clock input, I = Input, O = output, P = power supply connection
2 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
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ICS673-01 PLL Building Block
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature Soldering Temperature Storage temperature Operating Voltage, VDD Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Power Down Supply Current, IDDPD Short Circuit Current Input Capacitance Output Clock Frequency (4.5 to 5.5 V) Output Clock Frequency (3.13 to 3.46 V) CLK1 and CLK2 skew Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle VCO Gain, Kv Charge Pump Current, Ic Notes: Conditions Referenced to GND Referenced to GND ICS673M-01 ICS673M-01I Max of 10 seconds Minimum Typical Maximum 7 VDD+0.5 70 85 260 150 5.50 0.8 VDD 0 2.4 0.4 VDD-0.4 15 6 100 5 2 2 135 100 500 1.5 1.5 55 Units V V C C C C V V V V V V V V mA A mA pF MHz MHz ps ns ns % MHz/V A
ABSOLUTE MAXIMUM RATINGS (note 1) n
-0.5 0 -40 -65 3.13 2
DC CHARACTERISTICS (VDD = 5.0 V unless noted)
All except VCOIN All except VCOIN VCOIN VCOIN
IOH=-25mA IOL=25mA IOH=-8mA No Load,CLK1=40MHz No Load Each output OE, PD, SEL CLK1 with SEL=1 CLK1 with SEL=1 Rising edges at VDD/2 0.8 to 2.0V 2.0 to 0.8V At VDD/2
AC CHARACTERISTICS (VDD = 5.0 V unless noted)
45
50 95 2.4
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
3 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
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ICS673-01 PLL Building Block
External Components
The ICS673 requires a minimum number of external components for proper operation. A decoupling capacitor of 0.01F should be connected between VDD and GND as close to the ICS673 as possible. A series termination resistor of 33 may be used for each clock output. Two ceramic capacitors and a resistor are needed for the external loop filter; calculations to determine the proper values are shown on the following pages. The capacitors must have very low leakage, therefore high quality ceramic capacitors are recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is converted directly to voltage noise on the VCO input. +3.3 or 5 V C2 0.1F RZ C1
SEL OE PD VDD CHGP VCOIN CAP CLK1
Explanation of Operation
The ICS673 is a PLL building block circuit that includes an integrated VCO with a wide operating range. While it can easily lock MHz frequencies to other MHz frequencies, it is especially designed for starting with a kHz frequency and generating a frequency-locked MHz clock. Refer to Figure 1 below and to the Block Diagram on page 1. The phase/frequency detector compares the falling edges of the clocks connected to FBIN and REFIN. It then generates an error signal to the charge pump, which produces a charge proportional to this error. The external loop filter integrates this charge, producing a voltage that then controls the frequency of the VCO. This process continues until the edges of FBIN are aligned with the edges of the REFIN clock, at which point the output frequency will be locked to the input frequency.
200kHz
REFIN
40 MHz 20 MHz
ICS673-01
FBIN GND CLK2
200kHz
/100 Digital Divider or ICS674-01
Figure 1. Typical Configuration; Generating 40 MHz from 200 kHz
4 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
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ICS673-01 PLL Building Block
Determining the Loop Filter Values
The loop filter components consist of C1, C2, and RZ. Calculating these values is best illustrated by an example. Using the example in Figure 1, we can synthesize 40 MHz from a 200 kHz input. The phase locked loop may be approximately described by the following equations: Natural frequency, n = Kv * Ic N * C1 Equation 1 Choosing a damping factor of 0.7, Equation 2 becomes 0.7 = Rz 95 * 2.4 * 270 * 10 E - 12 2 200
and Rz = 79.8 k (82 k nearest std. value). The capacitor C2 is used to damp transients from the charge pump and should be at least 20 times smaller than C1, i.e., C2 C1/20. Therefore, C2 = 13.5 pF (13 pF nearest std. value). To summarize, to generate 40 MHz from 200 kHz with standard values, the loop filter components are: C1 = 270 pF C2 = 13 pF Rz = 82 k In general, making C1 larger may give improved loop performance, since it both lowers the bandwidth and increases the damping factor. However, it also increases the time for the loop to lock since the charge pump current has to charge a larger capacitance. When choosing either CLK1 or CLK2 to drive the feedback divider, CLK2 should be used whenever possible. See the following section, "Avoiding PLL Lockup", for additional explanations.
Damping factor, =
Rz 2
Kv * Ic * C1 Equation 2 N
where Kv = VCO gain (MHz/Volt) Ic = Charge pump current (A) N = Total feedback divide C1 = Loop filter capacitor (Farads) Rz = Loop filter resistor (Ohms) The natural frequency, n, is approximately equal to the bandwidth (in radians/sec). As a general rule, the bandwidth should be at least 10 times less than the reference frequency, i.e., n 2*BW REFIN/10. In this example, BW = REFIN/20, giving a bandwidth of 10 kHz. Using the first equation, C1 can be determined since all other variables are known. In the example of Figure 1, N = 200, comprising a divide-by-2 on the chip and the external divide-by-100. Therefore, Equation 1 becomes 2*10,000 = 95 * 2.4 200 * C1
and C1 = 289 pF (270 pF nearest std. value). 5 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
MDS 673-01 D
ICS673-01 PLL Building Block
250
VCO Frequency (MHz)
200
Nominal Minimum Characterization Value
150
Specification Limit
100
50
0
0.5
1.5
2.5
3.5
4.5
VCOIN
(V)
Figure 2. VCO Frequency vs Input Voltage at VDD = 5 V.
200 180
Nominal
VCO Frequency (MHz)
160 140 120 100 80 60 40 20 0
Specification Limit Minimum Characterization Value
0.4
0.8
1.2
1.6
2.4
2.8
3.2
VCOIN
(V)
Figure 3. VCO Frequency vs Input Voltage at VDD = 3.3 V.
6 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
MDS 673-01 D
3.6
0
2
5.5
0
1
2
3
4
5
ICS673-01 PLL Building Block
Avoiding PLL Lockup
In some applications, the ICS673 can "lock up" at the maximum VCO frequency. This is usually caused by power supply glitches or a very slow power supply ramp. This situation also occurs if the external divider starts to fail at high input frequencies. The usual failure mode of a divider circuit is that the output of the divider begins to miss clock edges. The phase detector interprets this as a too low output frequency and increases the VCO frequency. The feedback divider begins to miss even more clock edges, and the VCO frequency is continually increased until it is running at the maximum. Whether caused by power supply issues or by the external divider, the loop can only recover by powering down the circuit, asserting PD, or shorting the loop filter to ground. The simplest way to avoid this problem is to use an external divider that always operates correctly regardless of the VCO speed. Figures 2 and 3 show that the VCO is capable of high speeds. By using the internal divide-by-four and/or the CLK2 output, the maximum VCO frequency can be divided by 2, 4, or 8 and a slower counter can be used. Using the ICS673 internal dividers in this manner does reduce the number of frequencies that can be exactly synthesized by forcing the total VCO divide to change in increments of 2, 4, or 8. If this lockup problem occurs, there are several solutions, three of which are described below. 1.If the system has a reset or power good signal, this should be applied to the PD pin, forcing the ICS673 to stay powered down until the power supply voltage has stabilized. 2.If no power good signal is available, a simple power-on reset circuit can be attached to the PD pin, as shown in Figure 4 below. When the power supply ramps up, this circuit holds PD
MDS 673-01 D
asserted (device powered down) until the capacitor charges up.
VDD ICS673-01 PD C3 R1
A. Basic Circuit
VDD ICS673-01 PD C3 R1 D1
B. Faster Discharge Figure 4. Power-on Reset Circuits.
The circuit of Figure 4A is adequate in most cases, but the discharge rate of capacitor C3 when VDD goes low is limited by R1. As this discharge rate determines the minimum reset time, the circuit of Figure 4B may be used when a faster reset time is desired. The values of R1 and C3 should be selected to ensure that PD stays below 1.0 V until the power supply is stable. 3.A comparator circuit may be used to monitor the loop filter voltage, as shown in Figure 5. This circuit will dump the charge off the loop filter by asserting PD if the VCO begins to run too fast, and the PLL can recover. A good choice for this comparator is the National Semiconductor LMC7211BIM5X. It is low
7 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
ICS673-01 PLL Building Block
Avoiding PLL Lockup (continued)
power, very small (SOT-23), low cost, and has high input impedance. The trigger voltage of the comparator is set by the voltage divider formed by R2 and R3. The
ICS673-01 CHGP VCOIN VDD R2 RZ C2 C1 CAP
voltage should be set to a value higher than the VCO input is expected to run during normal operation. Typically, this might be 0.5 V below VDD. Hysteresis should be added to the circuit by connecting resistor R4.
PD
+
R4
R3
Figure 5. Using an External Comparator to Reset the VCO.
8 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
MDS 673-01 D
ICS673-01 PLL Building Block
Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Symbol A
A1
E
INDEX AREA
H
B
C
1
2
D A1 e C
h x 45
D E e H h L
Inches h Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.3859 0.3937 0.1497 0.1574 .050 BSC S 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500
Millimeters m Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 9.80 10.00 3.80 4.00 1.27 BSC S 5.80 6.20 0.25 0.50 0.41 1.27
A L
B
Ordering Information
Part/Order Number ICS673M-01 ICS673M-01T ICS673M-01I ICS673M-01IT Marking ICS673M-01 ICS673M-01 ICS673M-01I ICS673M-01I Shipping packaging tubes tape and reel tubes tape and reel Package 16 pin SOIC 16 pin SOIC 16 pin SOIC 16 pin SOIC Temperature 0 to 70 C 0 to 70 C -40 to 85 C -40 to 85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorpor ated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
9 Revision 022500 Printed 11/15/00 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126*(408)295-9800tel * www.icst.com
MDS 673-01 D

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